1. Field of the Invention
The present invention relates to DRAM, and more specifically, to an apparatus and method for controlling refreshing of and accessing to DRAM.
2. Related Art
Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM) are commonly used memory today. SRAM is a traditional type of memory with static access capability, which has good performance and simpler interface. As compared to SRAM that generally needs six transistors to store one bit, DRAM only needs one transistor and one capacitor to store one bit, thus having simpler structure and higher storage density. However, since DRAM stores data by utilizing charges stored in the capacitor and the capacitor needs to be charged periodically to prevent leakage of electricity, DRAM requires a refresh circuit to periodically refresh storage cell to ensure that stored data will not get lost. There is no need to perform refreshing in SRAM.
During the process of refreshing a DRAM, target memory bank of the refresh operation must be different from the one on which a read/write operation is currently conducted, that is, a refresh operation and an access operation can not be performed on a same memory bank simultaneously. Here, memory bank is the minimal unit which can NOT accept both access and refresh operation at one time slot. Many algorithms have been proposed in the art to make refresh confliction as less as possible. However, in practice, refresh confliction can not be fully prevented and eliminated by merely optimizing refresh policy.
Since refresh confliction is always inevitable, time delay in reading data in a DRAM is un-fixed. For example, in a worst case, user continuously reads a same memory bank via a series of access commands. To maintain integrity of data in that memory bank, a refresh controller of the DRAM will issue a mandatory refresh command and insert the command into the access command sequence. Thus, the series of access commands will be interrupted, and access operation on that memory bank will not be resumed until refresh operation is completed. That is, in case that there is refresh-access confliction, the memory bank first performs mandatory refresh operation, and access operation will be resumed only after refresh operation is completed. Thus, access operation on data is delayed and read out time of data is prolonged. Therefore, in DRAM, data access time is un-fixed.
However, a variable data access time adds complexity in design of other components related to DRAM and brings additional overhead. Therefore, there is need for a DRAM that has fixed data access time like SRAM, while keeping its advantage of high density and low power consumption.